Trends in the design and manufacture of microelectronic dies, or integrated circuits (ICs), are toward increasing miniaturization, circuit density, robustness, operating speeds and switching rates, while reducing power consumption and defects in the ICs. ICs are made up of a tremendous number (e.g., millions) of devices (e.g., transistors, diodes, capacitors), with each component being made up of a number of delicate structures, manufactured through a number of process steps. As IC manufacturing technology continues to evolve and the manufacturing of smaller sized components and more compact ICs become reality, the delicate structures likewise become smaller, more compact, and correspondingly, more delicate.
Because of the delicate nature of these components, and because of the significant number of processing steps the IC can undergo during manufacturing (e.g. ion implantation, plasma etching, diffusion, etc.) a great potential exists for damage to these components. This in turn leads to defects and the potential failure of the IC.
One or more of the IC manufacturing stages involve plasma related processes. Plasma related process include, but are not limited to metal etch, interlayer dielectric etch, via etch and the like. Plasma related processing may lead to electrical charging of exposed IC structures (e.g., metallic lines), which in turn can damage to the aforementioned delicate structures on the wafer, e.g., through excessive charge build-up, and then subsequent electrical discharge.
A few techniques have been used to estimate the charge resulting from the manufacturing process, including the use of a separate electrically erasable programmable read only memory (EEPROM) transistor that is placed in the processing chamber to sense the induced charge that may result from plasma related processing of the ICs. These current sensors have a number of deficiencies. The EEPROM sensors are not native to the process in which it is used to monitor. Rather, it is fabricated in a different process. Further, it is not typically located on the wafer being processed. The EEPROM sensors thus cannot sense the maximum charging signal as seen by the gate oxide in the MOSFETs located on the wafer being processed.
Moreover, the EEPROM sensor can only monitor for a brief period, then it must be pulled from the chamber and separately analyzed, which is ultimately time and resource consuming. Finally, inserting and removing the EEPROM sensor from the processing chamber creates the unnecessary potential for contamination of the process and equipment.
To minimize damage from excessive charge build up and discharge, it would be advantageous to monitor the ICs during the manufacturing process to determine the actual charging signal as seen by the gate oxide layer (in a MOSFET) or other delicate structures. A high charging signal will result in an abnormal degradation of the gate oxide layer (in a MOSFET), which in turn will result in undesirable gate leakage and a defective IC. Detecting the charging signal enables one to evaluate and make corrective modifications to equipment, recipes, materials, and other components of the IC manufacturing process (e.g. contamination, excessive exposure, etc.).
A real time sensor method and apparatus is therefore needed. Preferably, it can detect the maximum charge signals induced by the IC manufacturing processes under the precise conditions and recipes as the ICs being produced in the process. A charging sensor is also needed that can not only detect the charging signal over the entire charging-sensitive insulator (e.g. gate oxide), but also locally at the various regions of the charging-sensitive insulator where there is overlap with active regions of the substrate active body (e.g. the overlap region between either the source, drain or channel and the gate oxide in the case of a MOSFET).